For ESD enhancement each integrated circuit are not only provided with protection circuits to the I/O pads on the chip, but also inserted with power-rail ESD clamp circuits between the internal power wires and the internal ground wires thereof. Typically, for better ESD performance, the power-rail ESD clamp circuits are prepared at every distance of the internal wires. The shorter or the wider the internal power wire or the internal ground wire is, the better the ESD performance is.
However, the arrangement of power-rail ESD clamp circuits is always limited by the layout of integrated circuit. As shown in FIG. 1, an LCD source driver 10 has a rectangular top plane, and for plenty of output channels, there is always a long margin thereof to provide for output pads 14. Therefore, this long margin has no other space for arrangement of power-rail ESD clamp circuits 16, and the power wires and the ground wires 18 for the output pads 14 must extend along with the edge of the device area 12 to the power-rail ESD clamp circuits 15 on the short margin, even to the power-rail ESD clamp circuits 16 on the opposite long margin. The LCD source driver 10 shown in FIG. 1 is just for illustration, the ratio of the long margin to the short margin in a real LCD source driver 10 is much greater than 10:1, usually 13-17:1. Namely, the power wires and the ground wires 18 for the middle output pads 14 are much longer, causing poor ESD performance. To improve the ESD performance, conventionally, the widths of the power wires and the ground wires 18 are made wider, or the chip area of the power-rail ESD clamp circuits 16 are enlarged. However, either one of them will increase the chip size of the LCD source driver 10. Moreover, the development of LCD source driver is toward high pin count, and the shape of LCD source driver becomes longer as the number of output channels increases. If the chip is still designed as the conventional manner, the ESD performance will be worse and worse.
Therefore, it is desired an LCD source driver having improved ESD performance without increasing chip area.